MIPS Basis

1. Introduction

CISC: complex instruction set computer; e.g. x86-64

RISC: reduced instruction set computers

MIPS: Microprocessor without Interlocked Pipeline Stages; a typical RISC

5-Stage Pipeline

• Fetch instruction
• Read registers
• Arithmetic operation
• Memory access
• Write back

Compare to x86-64

Branch Delay Slot is visible too software to provide the possibility of optimization at upper-level:

No branch prediction!

2. Registers

There are 32 general-purpose registers for your program to use: $0 to $31.

• $0 Always returns zero, no matter what you store in it.
• $31 Is always used by the normal subroutine-calling instruction jal for the return address.
  • jalr can use any register for the return address

The floating-point math coprocessor (floating-point accelerator, or FPU), if available, adds 32 floating-point registers; in simple assembly language, they are called $f0 to $f31.

3. Passing Arguments

4. Data Types

5. Coprocessor 0

mtc0    <register s of CPU>, <n_th register of CP0> # Move to coprocessor 0
mfc0    d, $n   # d is loaded with the values from CPU control register number n

mfc0    t0, SR  # Status Register
and     t0, <complement of bits to clear>
or      t0, <bits to set>
mtc0    t0, SR

6. Address Layout

7. Instructions

lw $1, offset($2)

lb $1, offset($2)   # load byte with sign extension
lbu $1, offset($2)  # load byte with zero extension

Add

Count leading zeros / ones

Multiply / Divide

Multiply and Add / Subtract

Unsigned / Signed compare, less than

Branch

Load / Save

Load Linked / Store Conditional

Logical

7.1 Directives

7.2 Pseudo-instruction

7.3 Syscall

8. Exception

Synchronous exception:

• Traps: system call, break point, trap instruction → return to the next instruction

• Faults: page fault → re-execute the instruction; Recoverable

• Aborts: parity error (parity, the evenness or oddness of an integer; results from irregular changes to data), machine check → exit

Asynchronous exception:

• Interrupt: IO Interrupt, hard reset, soft reset

Status Register

Cause Register

9. Virtual Memory

9.1 Page Fault

Faults: page fault → re-execute the instruction; Recoverable

Address Translation:

9.2 Memory Management

Virtual Page, Physical Page, Address Translation and Shared Library

Protection: Access Permission

Translation Lookaside Buffer

9.3 MIPS Memory Management

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Last update: September 8, 2021

Authors: Co1lin